An IC is typically placed in one or more IC packages within a packaging hierarchy to form a working electronic device. For example, an IC can be initially placed in a first level IC package such as a single-chip module (“SCM”) or a multi-chip module (“MCM”), which, in turn, can be placed in a second level IC package such as a printed circuit board (“PCB”). The PCB including the IC can then be placed in a third level IC package such as a motherboard.
As the complexity of ICs has increased, the complexity of IC packages has also increased. IC packages are nowadays typically designed using computer aided design (“CAD”) tools, such as one available from Cadence Design Systems, Inc. (“Cadence”). Using such a CAD tool, an IC package can be designed to include various components within one or more layers. Vias can be used to connect different layers of the IC package. Typically, a via refers to a conductive pathway that connects two or more conductive layers of an IC package.
FIG. 1 illustrates a schematic of an IC package 100 that can be designed using a CAD tool of the prior art. In particular, FIG. 1 illustrates a top-sectional view of a layer of the IC package 100, which includes a via 102 and a trace 104 that is connected to the via 102. The via 102 includes a channel 106, which serves as a conductive pathway that connects the trace 104 to another trace (not illustrated) within a different layer of the IC package 100. The via 102 also includes a via pad 108, which serves as a conductive structure that connects the trace 104 to the channel 106. As illustrated in FIG. 1, the via pad 108 has a generally circular outer contour that intersects the trace 104 to define junctions 110 and 112. During manufacturing and subsequent use of the IC package 100, the “sharp” transitions associated with the junctions 110 and 112 can present a number of disadvantages. In particular, the junctions 110 and 112 can serve as traps during an etching process and can have a tendency to deteriorate over time. Also, the connection between the trace 104 and the channel 106 can be prone to fail in the event of mis-alignment of the channel 106 towards either of the junctions 110 and 112. Accordingly, to provide a more robust and reliable connection between the trace 104 and the channel 106, attempts have been made to design the via pad 108 so as to “smooth out” or “taper out” the junctions 110 and 112. This process is sometimes referred to as “adding a teardrop” or “tear dropping”, since the resulting via pad 108 with the added teardrop typically has an outer contour that is similar to that of a teardrop. During manufacturing, the resulting via pad 108 with the added teardrop is typically formed by including additional conductive material at or near the junctions 110 and 112.
Previous attempts for adding teardrops to a design of an IC package sometimes required a user to scan the design and manually add the teardrops at various places in the design. In light of the increased complexity of IC packages, such attempts can be tedious, time-consuming, and prone to inconsistencies or errors. While some attempts have been made to automate tear dropping for a design of an IC package, such attempts typically suffered from a notable disadvantage. In particular, such attempts typically added a teardrop to the design by defining extensions or branches of a trace to create the teardrop. However, such extensions can cause the design to misrepresent an electrical length of the trace. Typically, an electrical length of a transmission channel, such as the trace, refers to an effective length encountered by an electrical signal propagating through the transmission channel. In some instances, an electrical length of a transmission channel can be expressed as a physical length of the transmission channel multiplied by a factor that depends on a dielectric constant of the transmission channel. Extensions of the trace can be interpreted by a CAD tool as an increase in the electrical length of the trace, which increase is typically not observed in an actual IC package that is manufactured with the added teardrop. In particular, extensions of the trace can introduce errors of as much as 3 to 4 picoseconds in terms of signal propagation delays. As can be appreciated, misrepresentation of the electrical length of the trace can present a number of disadvantages, such as when using a CAD tool to verify that the design satisfies timing constraints or other design requirements. For example, misrepresentation of the electrical length of the trace can cause trace length matching computations to be erroneous. In some instances, it is desirable to perform trace length matching computations to a particular level of accuracy, such as to within 1 to 2 picoseconds in terms of signal propagation delays. Unfortunately, such level of accuracy may not be achievable in light of the errors that are introduced with the added teardrop.
It is against this background that a need arose to develop the apparatus, system, and method described herein.